FIG. 1 shows a schematic diagram of a typical phase lock loop (PLL) circuit employing a charge pump. A typical PLL circuit 100 consists of a phase frequency detector (PFD) 104 which detects a phase error, via a phase comparison, between a reference clock signal, denoted as REF_CLK, and a divided output clock from a divide-by-N divider 124. The PFD 104 generates and outputs UP and DOWN signals which drive a charge pump 106. The charge pump 106 injects a charge proportional to the detected phase error into a loop filter 116. The loop filter 116 then generates a control voltage Vctrl (or current) that is an input to a voltage (or current) controlled oscillator (VCO) 122. The VCO 122 generates a VCO output signal, denoted as VCO_CLK, whose frequency is proportional to the control voltage Vctrl. It should be noted that the PFD 104 is clocked by the reference clock signal REF_CLK; i.e. the phase comparisons occur at the reference frequency interval.
The reference clock signal REF_CLK is a function of a clock signal from an external reference oscillator (not shown) and may be a fraction of the external reference oscillator frequency, the fraction being derived by a divider (not shown) in a path between the external reference oscillator and the PFD 104.
In a locked condition, the UP and DOWN pulses are of substantially equal duration and no net charge is injected into the loop filter 116. Hence the control voltage Vctrl (or current) is ideally at a constant value which ensures that the VCO output signal VCO_CLK is at a constant frequency. The loop filter 116 typically accumulates a charge to produce a filtered control voltage that adjusts the VCO 122 output frequency.
The loop filter 116 is shown to include a first order loop filter implementation that comprises a series combination of a resistor (RFILT) 118 and a capacitor (CFILT) 120 in parallel with the charge pump 106 output. The loop filter 116 is only exemplary and may also include other components. For example, commonly an extra pole capacitor (not shown) is placed in parallel with the charge pump 106 output. The extra pole capacitor may be 1/10 the value of capacitor 120. The extra pole capacitor does not affect PLL 100 settling time or loop stability, but improves reference spur rejection in the VCO 122 output signal.
The charge pump 106 includes current sources 108 and 114 and switches 110 and 112. The switch 110 when closed passes the UP pulse to the loop filter 1 16. The switch 112 passes the DOWN pulse to the loop filter 116 when closed. The output of the PFD 104 controls the charge pump 106 so as to increase or decrease the control voltage Vctrl (or current) to the VCO 122 input.
FIG. 2 shows a set of waveforms 200 for a reference clock signal REF_CLK, a divider clock signal DIV_CLK, a VCO 122 output signal VCO_CLK, UP and DOWN pulses from phase-frequency detector PFD 104, and a control voltage Vctrl “noise” associated with the PLL circuit 100 of FIG. 1. The waveform of the control voltage Vctrl illustrates that noise from the charge pump and preceding blocks may affect the time jitter of the VCO 122 output signal VCO_CLK. The waveform of the control voltage Vctrl is measured at a node Vctrl of the loop filter 116. The loop filter 116 output voltage is the control signal to the VCO 122, and any disturbances on this signal result in increased jitter (in the time domain) or increased phase noise (in the frequency domain) at the VCO 122 output. Jitter/phase noise can be random or deterministic depending on the source of the disturbance. Examples of such activity may be device noise in the charge pump 116, power supply (VDD) white noise or switching noise, periodic or random noise coupling into the charge pump 116 from surrounding analog and digital circuits.
In current nanometer processes, the leakage and noise currents of a transistor can be quite significant. The charge pump 106 within PLL 100 is typically implemented using transistor based current sources that are turned on for the duration of the UP or DOWN pulses and are turned off otherwise. However the leakage current of these transistors can introduce noise from the VDD and GND connections to the charge pump 116 even when the charge pump current sources are turned off. The noise current introduces voltage “noise” on the control voltage Vctrl to the voltage controlled oscillator (VCO 122) which manifests as a combination of deterministic and random jitter (depending on the noise source) in the time domain or phase noise/reference spurs in the frequency domain on the VCO 122 output signal VCO_CLK. The jitter effects can be undesirable depending on the target application. The undesirable jitter effects are further exacerbated in low voltage designs that typically use high voltage or current gain VCO architectures to maximize the tuning range (i.e. to generate a wide range of frequencies from a limited control voltage or current range). With greater tuning range in the VCO 122, the output noise of charge pump 116, INOISE, will introduce more time jitter to the VCO_CLK signal.
In one solution to lower the charge pump leakage current and output noise, thick-oxide transistors are employed in the charge pump. However, the option of using thick-oxide transistors may not be available in a particular integrated circuit process technology or may require the use of costly extra mask process steps. In another solution, a large loop capacitance and power supply decoupling capacitance are used to minimize voltage noise for a given output noise current which results in an integrated circuit area, slow PLL settling time, and die cost penalty.
There is therefore a need to mitigate charge pump output noise current without the expense of thick oxide transistors or a large loop capacitor on-chip and to minimize the integrated circuit cost and die area penalty for improved VCO output time jitter and phase noise.